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Microprocessor and Memory Technologies Group
MC68LC302
Product Brief
Low Cost Integrated Multiprotocol Processor
Motorola introduces the low cost version of the well-known MC68302 Integrated Multiprotocol Processor (IMP). It will be known as the MC68LC302, and will expand a family of devices based on the MC68302. Some features and pins have been removed while other features have been enhanced as compared to the original MC68302. Simply put, the MC68LC302 is a traditional MC68302 with a new static 68000 core, a new timer and low power modes, but without the third serial communication controller (SCC). It is packaged in a low profile 100 TQFP that requires less board space than the regular MC68302, as well as making it suitable for use in height restricted applications such as PCMCIA.
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LOW POWER CONTROL
INTERRUPT CONTROLLER
1 GENERALPURPOSE DMA CHANNEL
3 TIMERS 4 CHIP SELECTS PIO SYSTEM CONTROL
RAM / ROM
STATIC M68000 CORE
68000 SYSTEM BUS 20 ADDRESS 8/16 DATA 1152 BYTES DUAL-PORT RAM
4 SDMA CHANNELS
PIT
RISC CONTROLLER
PERIPHERAL BUS
2 SERIAL CHANNELS (SCCs) 68LC302
SCP + 2 SMCs
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
SEMICONDUCTOR PRODUCT INFORMATION
(c) MOTOROLA, 1995
FEATURES
The features of the MC68LC302 are as follows. Bold face items show major differences from the MC68302. * On-Chip Static 68000 Core Supporting a 16- or 8-Bit M68000 Family System * SIB Including: -- Independent Direct Memory Access (IDMA) Controller -- Interrupt Controller with Two Modes of Operation -- Parallel Input/Output (I/O) Ports, Some with Interrupt Capability -- On-Chip 1152-Byte Dual-Port RAM -- Three Timers Including a Watchdog Timer -- New Periodic Interrupt Timer (PIT) -- Four Programmable Chip-Select Lines with Wait-State Generator Logic -- Programmable Address Mapping of the Dual-Port RAM and IMP Registers -- On-Chip Clock Generator with Output Signal -- On-Chip PLL Allows Operation with 32 kHz or 4 MHz Crystals -- Glueless Interface to EPROM, SRAM, Flash EPROM, and EEPROM -- Allows Boot in 8-bit Mode, and Running Switch to 16-bit Mode -- System Control: System Status and Control Logic Disable CPU Logic (Slave Mode Operation) Hardware Watchdog New Low-Power (Standby) Modes with Wake-Up from Two Pins or PIT Freeze Control for Debugging (Available Only in the PGA Package) DRAM Refresh Controller * CP Including: -- Main Controller (RISC Processor) -- Two Independent Full-Duplex Serial Communications Controllers (SCCs) -- Supporting Various Protocols: High-Level/Synchronous Data Link Control (HDLC/SDLC) Universal Asynchronous Receiver Transmitter (UART) Binary Synchronous Communication (BISYNC) Transparent Modes Autobaud Support V.110 Rate Adaption -- Four Serial DMA Channels for the Two SCCs -- Flexible Physical Interface Accessible by SCCs Including: -- Motorola Interchip Digital Link (IDL) General Circuit Interface (GCI, Also Known as IOM-21) Pulse Code Modulation (PCM) Highway Interface Nonmultiplexed Serial Interface (NMSI) Implementing Standard Modem Signals -- SCP for Synchronous Communication -- Two Serial Management Controllers (SMCs) to Support IDL and GCI Auxiliary Channels * 100 Pin Thin Quad Flat Pack (TQFP) Packaging
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IOM is a trademark of Siemens AG MC68LC302 PRODUCT INFORMATION MOTOROLA
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MC68LC302 APPLICATIONS
The MC68LC302 excels in several applications areas. First, any application using the MC68302,but not needing all three serial channels is a potential candidate for the MC68LC302. Note however, that the MC68LC302 sacrifices most of the provision for external bus mastership, thus the MC68LC302 may not be appropriate where the MC68302 is used as part of larger systems. Second, the MC68LC302 excels in low power and portable applications. The inclusion of a static 68000 core, coupled with the low power modes built into the device make it ideal for handheld, or other low power applications. The new 32 kHz or 4 MHz PLL option greatly reduces the total power budget of the designer's board, and allows the MC68LC302 to be an effective device in low power systems. The MC68LC302 can then optionally generate a full frequency clock for use by the rest of the board. During low power modes, the new periodic interrupt timer (PIT) allows the device to awaken at regular intervals. In addition, two pins can awaken the device from low power modes. Third, given that the MC68LC302 is packaged in a 100TQFP package, it allows the MC68LC302 to be used in space critical applications, as well as height critical applications such as PCMCIA cards. Fourth, since the disable CPU mode (also known as slave mode) is still retained, the MC68LC302 can function as a fully intelligent DMA-driven peripheral chip containing serial channels, timers, chip selects, etc.
DIFFERENCES BETWEEN THE MC68LC302 AND MC68302
The MC68LC302 has some specific differences from the MC68302. Even though the functionality of the processor and the peripherals remain the same, some of the flexibility has been removed due to the pin reduction from 132 on the original MC68302, to 100 pins on the MC68LC302. The following features have been removed or modified from the MC68302 in order to make the MC68LC302 possible. * SCC3 and its baud rate generator (BRG3) are removed. * External masters are not able to take the bus away from the MC68LC302 through the normal bus arbitration scheme as these pins no longer exist. An external master can still maintain bus mastership through a simple scheme using the HALT pin. This restriction does not apply when using the MC68LC302 in CPU disabled mode (slave mode), in which case BR, BG, and BGACK are all available. * Although the Independent DMA (IDMA) is still available, the external IDMA request pins (DREQ, DACK, and DONE) have been eliminated. IDMA transfers can only originate under CPU control. * Four address lines have been eliminated, giving a total of 20 address lines. However, the MC68LC302 supports more than a 1 MB addressing range, since each of the four chip selects still decodes a 24-bit address. This allows addressing a total of 4 MB. * Since the function code pins and AVEC have been removed, interrupt acknowledgment to external devices is only provided on levels one, six, and seven. * The DDCMP protocol is no longer available for the SCCs. * The total list of pins removed is: A23-A20, FC2-FC0, AVEC, RMC, IAC, BERR, BR, BG, BGACK, BCLR, IACK1, IACK6, IACK7, DREQ, DACK, DONE, BRG1, FRZ, TOUT1, NC1, NC3, TCLK3, RTS3, CTS3, CD3, plus 5 power and ground pins.
MOTOROLA
MC68LC302 PRODUCT INFORMATION
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* The SCP pins are now muxed with PA8, PA9, and PA10. The TXD3, RXD3, and RCLK3 functions associated with SCC3 are eliminated. * The UDS, LDS, and R/W pins are not available except in slave mode, where they replace the IPL2-0 pins. Instead, the new pins WEH, WEL, and OE have been defined for glueless interfacing to memory. * PA12 is now muxed with the MODCLK pin, which is associated with the 32 KHz or 4 MHz PLL. The MODCLK pin is sampled after reset, and then becomes PA12. * New VCCSYN, GNDSYN, and XFC pins have been added in support of the on-chip PLL. * For purposes of emulation and development support only, a special 132 PGA version is supported. This version adds back the FC2-0, IAC, FRZ, and AVEC pins. The FC2-0 pins allow bus cycles to be distinguished between program and data accesses, interrupt cycles, etc. The IAC, FRZ, and AVEC pins are provided so that emulation vendors can quickly retrofit their existing MC68302 emulator designs to support the MC68LC302.
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MC68LC302 PRODUCT INFORMATION
MOTOROLA
MC68LC302 PIN DESCRIPTION
NMSI1/ ISDN I/F
RXD1/L1RXD TXD1/L1TXD RCLK1/L1CLK TCLK1/L1SY0/SDS1 CD1/L1SY1 CTS1/L1GR RTS1/L1RQ/GCIDCL
Address Bus
A1-A19
Chip Select
CS0/IOUT2 CS3-CS1
Data Bus
D0-D15
NMSI2/ PAIO
RXD2/PA0 TXD2/PA1 RCLK2/PA2 TCLK2/PA3 CTS2/PA4 RTS2/PA5 CD2/PA6 BRG2/SDS2/PA7
AS WEH/A0 WEL/WE DTACK OE
Bus Control
(UDS/A0) (LDS/DS) (R/W)
System Control
MC68LC302 Signals
RESET HALT BUSW DISCPU
PAIO/ SCP
SPRXD/PA8 SPTXD/PA9 SPCLK/PA10 MODCLKPA12
Interrupt Control TIMER/PBIO
TIN1/PB3 TIN2/PB5 TOUT2/PB6 WDOG/PB7 IPL0/IRQ1 (BR) IPL1/IRQ6 (BGACK) IPL2/IRQ7 (BG)
PB8 PB9 PB10 PB11
IQGND(2) IQVDD(2)
Clock
CLKO EXTAL XTAL XFC
Note: Pins in parenthesis () show functionality that is only available in slave mode when the CPU is disabled by asserting the DISCPU pin.
MOTOROLA
MC68LC302 PRODUCT INFORMATION
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Table 1. MC68LC302 Ordering Information
Package Type Pin Grid Array (RC Suffix) Thin Quad Flat Pack (PU Suffix) Operating Voltage 5V 5V 5V 5V 5V 3.3V 3.3V 3.3V 3.3V Frequency (MHz) 20 16.67 16.67 20 20 16.67 16.67 20 20 Temperature 0C to 70C 0C to 70C -40C to +85C 0C to 70C -40C to +85C 0C to 70C -40C to +85C 0C to 70C -40C to +85C Order Number MC68LC302RC20 MC68LC302PU16 MC68LC302CPU16 MC68LC302PU20 TBD MC68LC302PU16V MC68LC302CPU16V TBD TBD
Thin Quad Flat Pack (PU Suffix)
Table 2. Documentation
Document Title MC68302 User's Manual M68000 Family Programmer's Reference Manual The 68K Source The 68LC302 Addendum Order Number MC68302UM/AD M68000PM/AD BR729/D Contents Detailed information for design M68000 Family instruction set Independent vendor listing supporting software and development tools Describes the differences between the MC68302 and the MC68LC302
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
Literature Distribution Centers:
USA: Motorola Literature Distribution; P.O. Box 20912, Arizona 85036. EUROPE: Motorola Ltd.; European Literature Centre; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141 Japan. ASIA-PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.
SEMICONDUCTOR PRODUCT INFORMATION

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